1. Field of the Invention
The present invention relates generally to the design and testing of memory arrays for integrated circuits. More specifically, but without limitation thereto, the present invention relates to the design and testing of latch based random access memory (LBRAM) in an application-specific integrated circuit (ASIC).
2. Description of Related Art
The use of memory arrays in application-specific integrated circuits (ASICs) is increasing, and it is estimated that memory arrays will constitute 94 percent of the die area in the average application-specific integrated circuit by the year 2014. There is also an increase in the use of small memories, typically implemented as latch based random access memory (LBRAM). A typical application-specific integrated circuit design uses over 400 latch based random access memory arrays. A key issue with the use of such a large number of memory arrays is how to test the memory arrays for manufacturing defects without increasing the die area by an excessive amount.
Application-specific integrated circuits (ASICs) are susceptible to manufacturing defects that may cause the ASIC to malfunction, called faults. To determine whether an ASIC has faults, the ASIC is typically tested using automated test equipment (ATE) to detect and reject defective parts before shipment to a customer. The number of faults that may be detected by ATE using a test devised by the manufacturer is typically expressed as a percentage of the total number of possible faults and is called the fault coverage of the test. A high value of fault coverage is desirable to avoid the costs associated with delivering defective parts.